1. Field of the Invention
The present invention relates to user-programmable antifuse technology. More particularly, the present invention relates to methods for fabricating antifuse devices as a part of a CMOS integrated circuit fabrication process. Still more particularly, the present invention relates to an edgeless, self-aligned, differential oxidation enhanced and diffusion-controlled minimum-geometry antifuse and method of fabrication.
2. The Prior Art
Numerous processes for fabrication of antifuses are known in the prior art. Some of these processes may be easily integrated into already existing integrated circuit fabrication processes. Some antifuse elements incorporate a dielectric antifuse material which contains a nitride or oxide such as silicon nitride or silicon dioxide, either as a single layer, or as a part of a multilayer dielectric such as that described in U.S. Pat. No. 4,823,181 to Mohsen et al. and U.S. Pat. No. 4,899,205 to Hamdy et al. Such structures exhibit excellent leakage and reliability characteristics, and are thus preferred for user-programmable antifuse applications.
Polysilicon/ONO/N+ Diffusion antifuse (ONO represents a three layer sandwich of oxide-nitride-oxide which acts as the antifuse material layer) has long been the choice as a production antifuse structure and process, but this process has suffered lately because it is difficult to scale in both the active antifuse cell dimension and antifuse thickness control during processing. When the active antifuse cell dimension grows, the defect density of the product having the same population of antifuses increases--thus smaller antifuses have a lower defect density and are desirable. The defect density of the product also increases when the antifuse thickness is reduced and the bottom oxide of the antifuse is grown directly over the N+ diffusion area.